AMD Graphic Platform Engineering (GPE) team is seeking an experienced engineerto lead the dGPU bringup. As part of the GPE Systems Engineering team, theSilicon Bring-up Lead will be responsible for leading the bring-up and debugsupport of the latest graphics IP’s for AMD’s Fusion APU’s and DGPU’s. Thesuccessful candidate will be providing hardware-engineering support duringpre-silicon planning, post-silicon bring-up, validation and production ramp.
You will be involved in the pre-silicon and post-silicon phases of the design.In the pre-silicon phase, you will be leading planning activities and developingcreative solutions and processes to meet aggressive post-silicon scheduleswhile working intimately with silicon design engineers and platform designengineers. In the post-silicon phase, as prototypes are received, using yourpre-silicon knowledge, you will lead systems engineering and silicon designteams through the various phases of bring-up, validation and production rampwhile working in the laboratory debugging hardware issues. You will alsooccasionally assist the customer support services team address customer designissues, as needed. In essence, you will be the link between design and physicalsilicon. The right candidate will be required to work closely with silicondesign engineers as well as participate in and/or lead interdisciplinary teams(hardware, software, program management, customer engineering, operations,marketing and sales).
Responsibilities:
- dGPU bringup lead is key technical lead in the program core team to lead allthe engineering teams(asic design, board design, VBIOS, driver, diag, productengineering teams, etc) in the company to make the new tape out dGPU chipssuccess
- Drive global function teams (ASIC design, platform, driver, etc.)collaboration to enable all features and optimize performance and meet theprogram schedule
- Drive global function teams (ASIC design, platform, driver, etc.) to resolveall issues happen in bringup and validation
- Work with product engineering and characterization team to work out theclocks/voltages for dGPU and maximum yield and performance at given TDP
Requirements:
- B.S. or M.S. In EE or CS or equivalent is required
- Fluent verbal English required
- A minimum of 5+ years’ experience on ASIC NPI program
- Hands-on experience with any one of ASIC bring up, validation, characterization,product definition or program management
- Strong team work experience with difference functional teams
- Strong communication skills
- Strong leadership for technical or program driving
- Familiar with any of HW design, driver develop or ASIC design